/* ****************************************************************************** * * @file reg8835.h * @brief Header file for sy8835 microcontroller. * @ic sy8835 * * @version 1.0 * @date 2024/11/01 10:59:40 * @author Alex Xu * * Copyright (c) 2013-2099,Tkplusemi Technology Co.,Ltd. * All Rights Reserved * * History: * Revision Date Author Desc * 1.0.0 2024/11/01 Alex Xu build this file ****************************************************************************** */ #ifndef __REG3315_H__ #define __REG3315_H__ /*-------------------------PMU Registers------------------------------*/ #define FAULT_STA0 0x10 #define FAULT_STA1 0x11 #define FAULT_STA2 0x12 #define CHIP_STA 0x13 #define VOX_STA 0x14 #define VDPM_VDD_CHG_EN 0x20 #define CHG_VFLOAT_SET 0x21 #define CHG_ICC_SET 0x22 #define CHG_ITC_ITERM_SET 0x23 #define CHG_VPMID_SET 0x25 #define WDT1_CFG 0x26 #define WDT1_RST 0x5A #define BST_COMM_EN 0x27 #define VOX_CFG 0x37 #define I2CR_RST_CFG 0x35 #define POWER_LED_CTRL0 0x39 #define XSEN_CTRL 0x31 #define IRQ_EN0 0x40 #define IRQ_EN1 0x41 #define POWER_CTRL_CMD 0x4F #define SOFT_DAT5 0x5C /*------------------------ Ext SFR Registers -------------------------*/ /*------ GPIO/MFP Registers ------*/ #define P0_PU 0x00 #define P0_PD 0x01 #define P0_OD 0x02 #define P0_IE 0x03 #define P0_OE 0x04 #define P1_PU 0x07 #define P1_PD 0x08 #define P1_OD 0x09 #define P1_IE 0x0A #define P1_OE 0x0B #define P1_DRV0 0x0C #define MFP_CTL0 0x0E #define MFP_CTL1 0x0F #define GPIO_INT_EN0 0x22 #define GPIO_INT_EN1 0x23 sfr GPIO_FLAG0 = 0xE4; sfr GPIO_FLAG1 = 0xE5; /*------ PWM Registers ------*/ #define PWM_CTL 0x10 #define PWM_PRE 0x11 #define PWM_REL 0x12 sfr PWM0_CMP = 0xCE; sfr PWM1_CMP = 0xCF; sfr PWM2_CMP = 0xDE; sfr PWM3_CMP = 0xDF; /*------ LED Registers ------*/ #define LED_CTL 0x13 /*-------- ADC Registers --------*/ #define ADC_CTL0 0x30 sfr ADC_CTL1 =0xA3; sfr ADC_IntFlag =0xA4; #define ADC_CTL2 0x31 #define ADC_IntEn 0x32 #define ADC_CH0_L 0x35 #define ADC_CH0_H 0x36 #define ADC_CH1_L 0x37 #define ADC_CH1_H 0x38 #define ADC_CH2_L 0x39 #define ADC_CH2_H 0x3A #define ADC_CH3_L 0x3B #define ADC_CH3_H 0x3C #define ADC_CH4_L 0x3D #define ADC_CH4_H 0x3E #define ADC_OFFSET 0x59 #define ADC_GAIN 0x5A /*-------- SYS Registers --------*/ #define LDO08_CTL 0x50 #define LDO15_CTL0 0x51 #define LDO15_CTL1 0x52 #define HOSC_TRIM 0x53 #define CHIP_ID 0x70 #define CHIP_VER 0x71 #define CLKPRE 0x72 #define RST_CFG 0x73 #define IRQ_PIN_CFG 0x76 #define LDREG_PW 0x7F sfr RST_FLAG = 0xE1; sfr IRQ_FLAG = 0xE2; sfr CHIP_STAT = 0xE3; sfr SRST = 0xF7; sfr SFRADDR = 0xFE; sfr SFRDATA = 0xFF; /*------- FLASH Registers ------*/ #define FLASH_STA0 0x60 #define FLASH_STA1 0x61 #define FLASH_STA2 0x62 #define FLASH_CRCL 0x63 #define FLASH_CRCH 0x64 #define FLASH_INIT 0x65 #define FLASH_INTF0 0x66 #define FLASH_INTF1 0x67 #define FLASH_DAT0 0x68 #define FLASH_DAT1 0x69 #define FLASH_DAT2 0x6A #define FLASH_DAT3 0x6B #define FLASH_ADDL 0x6C #define FLASH_ADDH 0x6D #define FLASH_OPTEN 0x6E #define FLASH_DAT_KEY 0x6F //------------------------- SFR Registers ---------------------------- /*--- BYTE Register ---*/ sfr P0 = 0x80; sfr P1 = 0x90; sfr P2 = 0xA0; sfr P3 = 0xB0; sfr PSW = 0xD0; sfr ACC = 0xE0; sfr B = 0xF0; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr DPL1 = 0x84; sfr DPH1 = 0x85; sfr WDTREL = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr CKCON = 0x8E; sfr DPSEL = 0x92; sfr S2CON = 0x96; sfr S2BUF = 0x97; sfr S0CON = 0x98; sfr S0BUF = 0x99; sfr IEN2 = 0x9A; sfr S1CON = 0x9B; sfr S1BUF = 0x9C; sfr S1RELL = 0x9D; sfr S2RELL = 0x9E; sfr S2RELH = 0x9F; sfr S2IOCFG = 0xF1; sfr ADC_CTRL1 = 0xA3; sfr ADC_INT_FLAG = 0xA4; sfr OCP_CTL = 0xA7; sfr IEN0 = 0xA8; sfr IP0 = 0xA9; sfr S0RELL = 0xAA; sfr SOFT_DAT0 = 0xAB; sfr SOFT_DAT1 = 0xAC; sfr SOFT_DAT2 = 0xAD; sfr SOFT_DAT3 = 0xAE; sfr SOFT_DAT4 = 0xAF; sfr IEN1 = 0xB8; sfr IP1 = 0xB9; sfr S0RELH = 0xBA; sfr S1RELH = 0xBB; sfr IRCON2 = 0xBF; sfr IRCON = 0xC0; sfr ADCON = 0xD8; /*--- BIT Register ---*/ /* PSW */ sbit CY = 0xD7; sbit AC = 0xD6; sbit F0 = 0xD5; sbit RS1 = 0xD4; sbit RS0 = 0xD3; sbit OV = 0xD2; sbit P = 0xD0; /* TCON */ sbit TF1 = 0x8F; sbit TR1 = 0x8E; sbit TF0 = 0x8D; sbit TR0 = 0x8C; sbit IE1 = 0x8B; sbit IT1 = 0x8A; sbit IE0 = 0x89; sbit IT0 = 0x88; /* T2CON */ sbit T2PS = 0xCF; sbit I3FR = 0xCE; sbit I2FR = 0xCD; sbit T2R1 = 0xCC; sbit T2R0 = 0xCB; sbit T2CM = 0xCA; sbit T2I1 = 0xC9; sbit T2I0 = 0xC8; /* S0CON */ sbit SM0 = 0x9F; sbit SM1 = 0x9E; sbit SM20 = 0x9D; sbit REN0 = 0x9C; sbit TB80 = 0x9B; sbit RB80 = 0x9A; sbit TI0 = 0x99; sbit RI0 = 0x98; /* IEN0 */ sbit EAL = 0xAF;//global IRQ enable sbit WDT = 0xAE;//Watchdog timer refresh flag sbit ET2 = 0xAD;//Timer2 IRQ enable sbit ES0 = 0xAC;//Serial Port 0 sbit ET1 = 0xAB;//Timer1 overflow sbit EX1 = 0xAA;//External 1 sbit ET0 = 0xA9;//Timer0 overflow sbit EX0 = 0xA8;//External 0 /* IEN1 */ sbit EXEN2 = 0xBF;//Timer2 external reload sbit SWDT = 0xBE;//Watchdog timer start/refresh flag. sbit EX6 = 0xBD;//External 6 sbit EX5 = 0xBC;//External 5 sbit EX4 = 0xBB;//External 4 sbit EX3 = 0xBA;//External 3 sbit EX2 = 0xB9;//External 2 sbit EX7 = 0xB8;//External 7 /* IEN1 */ //sbit ES2 = 0x9B; //sbit ES1 = 0x9A; /* IRCON */ sbit EXF2 = 0xC7;//Timer 2 external reload flag sbit TF2 = 0xC6;//Timer 2 overflow flag sbit IEX6 = 0xC5;// sbit IEX5 = 0xC4;// sbit IEX4 = 0xC3;// sbit IEX3 = 0xC2;// sbit IEX2 = 0xC1;// sbit IADC = 0xC0;// /* ADCON */ sbit BD = 0xDF; /* P0 */ sbit P00 = P0^0; sbit P01 = P0^1; sbit P02 = P0^2; sbit P03 = P0^3; sbit P04 = P0^4; sbit P05 = P0^5; sbit P06 = P0^6; sbit P07 = P0^7; /* P0 */ sbit P10 = P1^0; sbit P11 = P1^1; sbit P12 = P1^2; sbit P13 = P1^3; sbit P14 = P1^4; sbit P15 = P1^5; //sbit P16 = P1^6; //sbit P17 = P1^7; #endif