306 lines
7.3 KiB
C
306 lines
7.3 KiB
C
/*
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******************************************************************************
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*
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* @file reg3315.h
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* @brief Header file for TP3315 microcontroller.
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* @ic sy8835
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*
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* @version 1.0
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* @date 2024/11/01 10:59:40
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* @author Alex Xu
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*
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* Copyright (c) 2013-2099,Tkplusemi Technology Co.,Ltd.
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* All Rights Reserved
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*
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* History:
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* Revision Date Author Desc
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* 1.0.0 2024/11/01 Alex Xu build this file
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******************************************************************************
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*/
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#ifndef __REG3315_H__
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#define __REG3315_H__
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/*-------------------------PMU Registers------------------------------*/
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#define FAULT_STA0 0x10
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#define FAULT_STA1 0x11
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#define FAULT_STA2 0x12
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#define CHIP_STA 0x13
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#define VOX_STA 0x14
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#define VDPM_VDD_CHG_EN 0x20
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#define CHG_VFLOAT_SET 0x21
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#define CHG_ICC_SET 0x22
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#define CHG_ITC_ITERM_SET 0x23
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#define CHG_VPMID_SET 0x25
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#define WDT1_CFG 0x26
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#define WDT1_RST 0x5A
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#define BST_COMM_EN 0x27
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#define VOX_CFG 0x37
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#define I2CR_RST_CFG 0x35
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#define POWER_LED_CTRL0 0x39
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#define XSEN_CTRL 0x31
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#define IRQ_EN0 0x40
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#define IRQ_EN1 0x41
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#define POWER_CTRL_CMD 0x4F
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#define SOFT_DAT5 0x5C
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/*------------------------ Ext SFR Registers -------------------------*/
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/*------ GPIO/MFP Registers ------*/
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#define P0_PU 0x00
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#define P0_PD 0x01
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#define P0_OD 0x02
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#define P0_IE 0x03
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#define P0_OE 0x04
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#define P1_PU 0x07
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#define P1_PD 0x08
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#define P1_OD 0x09
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#define P1_IE 0x0A
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#define P1_OE 0x0B
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#define P1_DRV0 0x0C
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#define MFP_CTL0 0x0E
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#define MFP_CTL1 0x0F
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#define GPIO_INT_EN0 0x22
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#define GPIO_INT_EN1 0x23
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sfr GPIO_FLAG0 = 0xE4;
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sfr GPIO_FLAG1 = 0xE5;
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/*------ PWM Registers ------*/
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#define PWM_CTL 0x10
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#define PWM_PRE 0x11
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#define PWM_REL 0x12
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sfr PWM0_CMP = 0xCE;
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sfr PWM1_CMP = 0xCF;
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sfr PWM2_CMP = 0xDE;
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sfr PWM3_CMP = 0xDF;
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/*------ LED Registers ------*/
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#define LED_CTL 0x13
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/*-------- ADC Registers --------*/
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#define ADC_CTL0 0x30
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sfr ADC_CTL1 =0xA3;
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sfr ADC_IntFlag =0xA4;
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#define ADC_CTL2 0x31
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#define ADC_IntEn 0x32
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#define ADC_CH0_L 0x35
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#define ADC_CH0_H 0x36
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#define ADC_CH1_L 0x37
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#define ADC_CH1_H 0x38
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#define ADC_CH2_L 0x39
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#define ADC_CH2_H 0x3A
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#define ADC_CH3_L 0x3B
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#define ADC_CH3_H 0x3C
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#define ADC_CH4_L 0x3D
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#define ADC_CH4_H 0x3E
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/*-------- SYS Registers --------*/
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#define LDO08_CTL 0x50
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#define LDO15_CTL0 0x51
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#define LDO15_CTL1 0x52
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#define HOSC_TRIM 0x53
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#define CHIP_ID 0x70
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#define CHIP_VER 0x71
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#define CLKPRE 0x72
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#define RST_CFG 0x73
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#define IRQ_PIN_CFG 0x76
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#define LDREG_PW 0x7F
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sfr RST_FLAG = 0xE1;
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sfr IRQ_FLAG = 0xE2;
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sfr CHIP_STAT = 0xE3;
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sfr SRST = 0xF7;
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sfr SFRADDR = 0xFE;
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sfr SFRDATA = 0xFF;
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/*------- FLASH Registers ------*/
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#define FLASH_STA0 0x60
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#define FLASH_STA1 0x61
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#define FLASH_STA2 0x62
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#define FLASH_CRCL 0x63
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#define FLASH_CRCH 0x64
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#define FLASH_INIT 0x65
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#define FLASH_INTF0 0x66
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#define FLASH_INTF1 0x67
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#define FLASH_DAT0 0x68
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#define FLASH_DAT1 0x69
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#define FLASH_DAT2 0x6A
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#define FLASH_DAT3 0x6B
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#define FLASH_ADDL 0x6C
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#define FLASH_ADDH 0x6D
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#define FLASH_OPTEN 0x6E
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#define FLASH_DAT_KEY 0x6F
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//------------------------- SFR Registers ----------------------------
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/*--- BYTE Register ---*/
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sfr P0 = 0x80;
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sfr P1 = 0x90;
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sfr P2 = 0xA0;
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sfr P3 = 0xB0;
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sfr PSW = 0xD0;
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sfr ACC = 0xE0;
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sfr B = 0xF0;
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sfr SP = 0x81;
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sfr DPL = 0x82;
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sfr DPH = 0x83;
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sfr DPL1 = 0x84;
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sfr DPH1 = 0x85;
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sfr WDTREL = 0x86;
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sfr PCON = 0x87;
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sfr TCON = 0x88;
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sfr TMOD = 0x89;
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sfr TL0 = 0x8A;
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sfr TL1 = 0x8B;
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sfr TH0 = 0x8C;
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sfr TH1 = 0x8D;
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sfr CKCON = 0x8E;
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sfr DPSEL = 0x92;
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sfr S2CON = 0x96;
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sfr S2BUF = 0x97;
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sfr S0CON = 0x98;
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sfr S0BUF = 0x99;
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sfr IEN2 = 0x9A;
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sfr S1CON = 0x9B;
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sfr S1BUF = 0x9C;
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sfr S1RELL = 0x9D;
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sfr S2RELL = 0x9E;
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sfr S2RELH = 0x9F;
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sfr S2IOCFG = 0xF1;
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sfr ADC_CTRL1 = 0xA3;
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sfr ADC_INT_FLAG = 0xA4;
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sfr OCP_CTL = 0xA7;
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sfr IEN0 = 0xA8;
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sfr IP0 = 0xA9;
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sfr S0RELL = 0xAA;
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sfr SOFT_DAT0 = 0xAB;
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sfr SOFT_DAT1 = 0xAC;
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sfr SOFT_DAT2 = 0xAD;
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sfr SOFT_DAT3 = 0xAE;
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sfr SOFT_DAT4 = 0xAF;
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sfr IEN1 = 0xB8;
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sfr IP1 = 0xB9;
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sfr S0RELH = 0xBA;
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sfr S1RELH = 0xBB;
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sfr IRCON2 = 0xBF;
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sfr IRCON = 0xC0;
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sfr ADCON = 0xD8;
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/*--- BIT Register ---*/
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/* PSW */
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sbit CY = 0xD7;
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sbit AC = 0xD6;
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sbit F0 = 0xD5;
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sbit RS1 = 0xD4;
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sbit RS0 = 0xD3;
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sbit OV = 0xD2;
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sbit P = 0xD0;
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/* TCON */
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sbit TF1 = 0x8F;
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sbit TR1 = 0x8E;
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sbit TF0 = 0x8D;
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sbit TR0 = 0x8C;
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sbit IE1 = 0x8B;
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sbit IT1 = 0x8A;
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sbit IE0 = 0x89;
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sbit IT0 = 0x88;
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/* T2CON */
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sbit T2PS = 0xCF;
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sbit I3FR = 0xCE;
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sbit I2FR = 0xCD;
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sbit T2R1 = 0xCC;
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sbit T2R0 = 0xCB;
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sbit T2CM = 0xCA;
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sbit T2I1 = 0xC9;
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sbit T2I0 = 0xC8;
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/* S0CON */
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sbit SM0 = 0x9F;
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sbit SM1 = 0x9E;
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sbit SM20 = 0x9D;
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sbit REN0 = 0x9C;
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sbit TB80 = 0x9B;
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sbit RB80 = 0x9A;
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sbit TI0 = 0x99;
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sbit RI0 = 0x98;
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/* IEN0 */
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sbit EAL = 0xAF;//global IRQ enable
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sbit WDT = 0xAE;//Watchdog timer refresh flag
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sbit ET2 = 0xAD;//Timer2 IRQ enable
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sbit ES0 = 0xAC;//Serial Port 0
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sbit ET1 = 0xAB;//Timer1 overflow
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sbit EX1 = 0xAA;//External 1
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sbit ET0 = 0xA9;//Timer0 overflow
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sbit EX0 = 0xA8;//External 0
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/* IEN1 */
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sbit EXEN2 = 0xBF;//Timer2 external reload
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sbit SWDT = 0xBE;//Watchdog timer start/refresh flag.
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sbit EX6 = 0xBD;//External 6
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sbit EX5 = 0xBC;//External 5
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sbit EX4 = 0xBB;//External 4
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sbit EX3 = 0xBA;//External 3
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sbit EX2 = 0xB9;//External 2
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sbit EX7 = 0xB8;//External 7
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/* IEN1 */
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//sbit ES2 = 0x9B;
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//sbit ES1 = 0x9A;
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/* IRCON */
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sbit EXF2 = 0xC7;//Timer 2 external reload flag
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sbit TF2 = 0xC6;//Timer 2 overflow flag
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sbit IEX6 = 0xC5;//
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sbit IEX5 = 0xC4;//
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sbit IEX4 = 0xC3;//
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sbit IEX3 = 0xC2;//
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sbit IEX2 = 0xC1;//
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sbit IADC = 0xC0;//
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/* ADCON */
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sbit BD = 0xDF;
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/* P0 */
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sbit P00 = P0^0;
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sbit P01 = P0^1;
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sbit P02 = P0^2;
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sbit P03 = P0^3;
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sbit P04 = P0^4;
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sbit P05 = P0^5;
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sbit P06 = P0^6;
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sbit P07 = P0^7;
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/* P0 */
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sbit P10 = P1^0;
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sbit P11 = P1^1;
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sbit P12 = P1^2;
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sbit P13 = P1^3;
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sbit P14 = P1^4;
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sbit P15 = P1^5;
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//sbit P16 = P1^6;
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//sbit P17 = P1^7;
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#endif |