/*--------------------------------------------------------------------- REG3310.H Header file for TP3310 microcontroller. Initial Released by zheng, 2023-12-01. Thinkplus Semiconductor co., ltd, All Rights Reserved! ----------------------------------------------------------------------*/ #ifndef __REG3310_H__ //给客户的头文件名里的所有内部项目编号需改成实际产品编号！！！ #define __REG3310_H__ //------------------------ Ext SFR Registers ------------------------- /*------ GPIO/MFP Registers ------*/ #define P0_PU 0x00 #define P0_PD 0x01 #define P0_OD 0x02 #define P0_DRV 0x03 #define P0_IE 0x05 #define P0_OE 0x06 #define P1_PU 0x07 #define P1_PD 0x08 #define P1_OD 0x09 #define P1_IE 0x0C #define P1_OE 0x0D #define MFP_CTL0 0x0E #define MFP_CTL1 0x0F #define GPIO_TEST 0x9B /*----- IRQ Enable Registers ----*/ #define IRQ_EN0 0x14 // Abnormal interrupt enable #define IRQ_EN1 0x15 // EXTI interrupt enable 0 #define IRQ_EN2 0x16 // EXTI interrupt enable 1 #define IRQ_EN3 0x17 // VOL/R LOADIN/ON interrupt enable #define IRQ_EN4 0x18 // VOL/R Recharge and IOFF interrupt enable #define IRQ_EN7 0x1B // KEY/PWM interrupt enable #define IRQ_EN9 0x1D // Charger interrupt enable #define IRQ_EN10 0x1E // VBUS/COMP/HALL/STBTMR/ADC_DATA_RDY interrupt enable /*--- Wakeup Enable Registers ---*/ #define WKUP_EN0 0x21 // BOOST/HALL/KEY/VBUS Wakeup enable #define WKUP_EN1 0x22 // EXTI and VOL/R Short Wakeup enable #define WKUP_EN3 0x24 // BAT_LOW/TMR/VOX LOADIN/ON Wakeup enable /*-------- ADC Registers --------*/ #define ADC_CTL0 0x29 #define ADC00 0x2D #define ADCCS_CTL0 0x4F /*---- OTP KEY Registers ----*/ #define OTP_KEY 0x8F /*------ VOL/R Registers -----*/ #define VOL_IOFF_TRIM 0x69 #define VOX_CON0 0x6A #define VOX_CON1 0x6B #define VOX_CON2 0x6C #define VOR_IOFF_TRIM 0x6D #define ST_VOX 0x6E /*------ CHG Registers ------*/ #define REG_CHG0 0x70 #define REG_CHG3 0x9D #define OTP_CHG0 0x71 #define OTP_CHG1 0x72 /*----- BOOST Registers -----*/ #define BST_CTL0 0x78 #define BST_CTL1 0x79 /*------ PMU Registers ------*/ #define PMU_CTL0 0x80 #define PMU_CTL1 0x81 #define PMU_CTL3 0x83 #define PMU_CTL6 0x86 #define PMU_CTL7 0x87 #define PMU_CTL8 0x88 #define PMU_CTL9 0x89 /*------ CMU Registers ------*/ #define HOSC_CTL 0x8B /*------ Misc Registers -----*/ #define CHIP_ID 0x8D #define CHIP_VER 0x8E //------------------------- SFR Registers ---------------------------- /*--- BYTE Register ---*/ sfr P0 = 0x80; sfr P1 = 0x90; sfr P2 = 0xA0; sfr P3 = 0xB0; sfr PSW = 0xD0; sfr ACC = 0xE0; sfr B = 0xF0; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr DPL1 = 0x84; sfr DPH1 = 0x85; sfr WDTREL = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr CKCON = 0x8E; sfr DPSEL = 0x92; sfr ASKCTL0 = 0x96; sfr ASKDATA = 0x97; sfr S0CON = 0x98; sfr S0BUF = 0x99; sfr IEN2 = 0x9A; sfr S1CON = 0x9B; sfr S1BUF = 0x9C; sfr S1RELL = 0x9D; sfr16 ADC_DAT = 0xA1; sfr ADC_DATL = 0xA1; sfr ADC_DATH = 0xA2; sfr ADC_OFFSET = 0xA3; sfr ADC_CTL1 = 0xA5; sfr IEN0 = 0xA8; sfr IP0 = 0xA9; sfr S0RELL = 0xAA; sfr REG_CHG1 = 0xB1; sfr REG_CHG2 = 0xB2; sfr CHG_CTL = 0xB3; sfr BST_EN = 0xB5; sfr VOX_CTL0 = 0xB7; sfr IEN1 = 0xB8; sfr IP1 = 0xB9; sfr S0RELH = 0xBA; sfr S1RELH = 0xBB; sfr IRCON2 = 0xBF; sfr IRCON = 0xC0; sfr CCEN = 0xC1; sfr CCL1 = 0xC2; sfr CCH1 = 0xC3; sfr CCL2 = 0xC4; sfr CCH2 = 0xC5; sfr CCL3 = 0xC6; sfr CCH3 = 0xC7; sfr T2CON = 0xC8; sfr CRCL = 0xCA; sfr CRCH = 0xCB; sfr TL2 = 0xCC; sfr TH2 = 0xCD; sfr CLKPRE = 0xD2; sfr RSTCON = 0xD3; sfr KEY_CTL = 0xD7; sfr ADCON = 0xD8; sfr RST_FLAG = 0xE1; sfr CHIP_STA0 = 0xE2; sfr CHIP_STA1 = 0xE3; sfr CHIP_STA2 = 0xE4; sfr CHIP_STA3 = 0xE5; sfr CHIP_STA4 = 0xE6; sfr IRQ_FLAG0 = 0xE8; sfr IRQ_FLAG1 = 0xE9; sfr IRQ_FLAG2 = 0xEA; sfr IRQ_FLAG3 = 0xEB; sfr IRQ_FLAG4 = 0xEC; sfr IRQ_FLAG7 = 0xEF; sfr IRQ_FLAG9 = 0xF2; sfr IRQ_FLAG10 = 0xF3; sfr SRST = 0xF7; sfr WKUP_FLAG0 = 0xF6; sfr WKUP_FLAG1 = 0xF8; sfr WKUP_FLAG3 = 0xFA; sfr SFRADDR = 0xFE; sfr SFRDATA = 0xFF; /*--- BIT Register ---*/ /* PSW */ sbit CY = 0xD7; sbit AC = 0xD6; sbit F0 = 0xD5; sbit RS1 = 0xD4; sbit RS0 = 0xD3; sbit OV = 0xD2; sbit P = 0xD0; /* TCON */ sbit TF1 = 0x8F; sbit TR1 = 0x8E; sbit TF0 = 0x8D; sbit TR0 = 0x8C; sbit IE1 = 0x8B; sbit IT1 = 0x8A; sbit IE0 = 0x89; sbit IT0 = 0x88; /* T2CON */ sbit T2PS = 0xCF; sbit I3FR = 0xCE; sbit I2FR = 0xCD; sbit T2R1 = 0xCC; sbit T2R0 = 0xCB; sbit T2CM = 0xCA; sbit T2I1 = 0xC9; sbit T2I0 = 0xC8; /* S0CON */ sbit SM0 = 0x9F; sbit SM1 = 0x9E; sbit SM20 = 0x9D; sbit REN0 = 0x9C; sbit TB80 = 0x9B; sbit RB80 = 0x9A; sbit TI0 = 0x99; sbit RI0 = 0x98; /* IEN0 */ sbit EAL = 0xAF; sbit WDT = 0xAE; sbit ET2 = 0xAD; sbit ES0 = 0xAC; sbit ET1 = 0xAB; sbit EX1 = 0xAA; sbit ET0 = 0xA9; sbit EX0 = 0xA8; /* IEN1 */ sbit EXEN2 = 0xBF; sbit SWDT = 0xBE; sbit EX6 = 0xBD; sbit EX5 = 0xBC; sbit EX4 = 0xBB; sbit EX3 = 0xBA; sbit EX2 = 0xB9; sbit EX7 = 0xB8; /* IRCON */ sbit EXF2 = 0xC7; sbit TF2 = 0xC6; sbit IEX6 = 0xC5; sbit IEX5 = 0xC4; sbit IEX4 = 0xC3; sbit IEX3 = 0xC2; sbit IEX2 = 0xC1; sbit IADC = 0xC0; /* ADCON */ sbit BD = 0xDF; /* P0 */ sbit P00 = P0^0; sbit P01 = P0^1; sbit P02 = P0^2; sbit P03 = P0^3; sbit P04 = P0^4; sbit P05 = P0^5; sbit P06 = P0^6; sbit P07 = P0^7; /* P1 */ sbit P10 = P1^0; #endif