278 lines
6.6 KiB
C
278 lines
6.6 KiB
C
/*---------------------------------------------------------------------
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REG3310.H
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Header file for TP3310 microcontroller.
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Initial Released by zheng, 2023-12-01.
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Thinkplus Semiconductor co., ltd, All Rights Reserved!
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----------------------------------------------------------------------*/
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#ifndef __REG3310_H__ //给客户的头文件名里的所有内部项目编号需改成实际产品编号！！！
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#define __REG3310_H__
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//------------------------ Ext SFR Registers -------------------------
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/*------ GPIO/MFP Registers ------*/
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#define P0_PU 0x00
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#define P0_PD 0x01
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#define P0_OD 0x02
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#define P0_DRV 0x03
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#define P0_IE 0x05
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#define P0_OE 0x06
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#define P1_PU 0x07
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#define P1_PD 0x08
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#define P1_OD 0x09
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#define P1_IE 0x0C
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#define P1_OE 0x0D
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#define MFP_CTL0 0x0E
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#define MFP_CTL1 0x0F
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#define GPIO_TEST 0x9B
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/*----- IRQ Enable Registers ----*/
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#define IRQ_EN0 0x14 // Abnormal interrupt enable
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#define IRQ_EN1 0x15 // EXTI interrupt enable 0
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#define IRQ_EN2 0x16 // EXTI interrupt enable 1
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#define IRQ_EN3 0x17 // VOL/R LOADIN/ON interrupt enable
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#define IRQ_EN4 0x18 // VOL/R Recharge and IOFF interrupt enable
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#define IRQ_EN7 0x1B // KEY/PWM interrupt enable
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#define IRQ_EN9 0x1D // Charger interrupt enable
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#define IRQ_EN10 0x1E // VBUS/COMP/HALL/STBTMR/ADC_DATA_RDY interrupt enable
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/*--- Wakeup Enable Registers ---*/
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#define WKUP_EN0 0x21 // BOOST/HALL/KEY/VBUS Wakeup enable
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#define WKUP_EN1 0x22 // EXTI and VOL/R Short Wakeup enable
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#define WKUP_EN3 0x24 // BAT_LOW/TMR/VOX LOADIN/ON Wakeup enable
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/*-------- ADC Registers --------*/
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#define ADC_CTL0 0x29
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#define ADC00 0x2D
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#define ADCCS_CTL0 0x4F
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/*---- OTP KEY Registers ----*/
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#define OTP_KEY 0x8F
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/*------ VOL/R Registers -----*/
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#define VOL_IOFF_TRIM 0x69
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#define VOX_CON0 0x6A
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#define VOX_CON1 0x6B
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#define VOX_CON2 0x6C
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#define VOR_IOFF_TRIM 0x6D
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#define ST_VOX 0x6E
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/*------ CHG Registers ------*/
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#define REG_CHG0 0x70
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#define REG_CHG3 0x9D
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#define OTP_CHG0 0x71
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#define OTP_CHG1 0x72
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/*----- BOOST Registers -----*/
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#define BST_CTL0 0x78
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#define BST_CTL1 0x79
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/*------ PMU Registers ------*/
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#define PMU_CTL0 0x80
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#define PMU_CTL1 0x81
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#define PMU_CTL3 0x83
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#define PMU_CTL6 0x86
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#define PMU_CTL7 0x87
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#define PMU_CTL8 0x88
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#define PMU_CTL9 0x89
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/*------ CMU Registers ------*/
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#define HOSC_CTL 0x8B
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/*------ Misc Registers -----*/
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#define CHIP_ID 0x8D
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#define CHIP_VER 0x8E
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//------------------------- SFR Registers ----------------------------
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/*--- BYTE Register ---*/
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sfr P0 = 0x80;
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sfr P1 = 0x90;
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sfr P2 = 0xA0;
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sfr P3 = 0xB0;
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sfr PSW = 0xD0;
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sfr ACC = 0xE0;
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sfr B = 0xF0;
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sfr SP = 0x81;
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sfr DPL = 0x82;
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sfr DPH = 0x83;
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sfr DPL1 = 0x84;
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sfr DPH1 = 0x85;
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sfr WDTREL = 0x86;
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sfr PCON = 0x87;
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sfr TCON = 0x88;
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sfr TMOD = 0x89;
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sfr TL0 = 0x8A;
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sfr TL1 = 0x8B;
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sfr TH0 = 0x8C;
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sfr TH1 = 0x8D;
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sfr CKCON = 0x8E;
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sfr DPSEL = 0x92;
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sfr ASKCTL0 = 0x96;
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sfr ASKDATA = 0x97;
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sfr S0CON = 0x98;
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sfr S0BUF = 0x99;
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sfr IEN2 = 0x9A;
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sfr S1CON = 0x9B;
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sfr S1BUF = 0x9C;
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sfr S1RELL = 0x9D;
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sfr16 ADC_DAT = 0xA1;
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sfr ADC_DATL = 0xA1;
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sfr ADC_DATH = 0xA2;
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sfr ADC_OFFSET = 0xA3;
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sfr ADC_CTL1 = 0xA5;
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sfr IEN0 = 0xA8;
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sfr IP0 = 0xA9;
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sfr S0RELL = 0xAA;
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sfr REG_CHG1 = 0xB1;
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sfr REG_CHG2 = 0xB2;
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sfr CHG_CTL = 0xB3;
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sfr BST_EN = 0xB5;
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sfr VOX_CTL0 = 0xB7;
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sfr IEN1 = 0xB8;
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sfr IP1 = 0xB9;
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sfr S0RELH = 0xBA;
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sfr S1RELH = 0xBB;
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sfr IRCON2 = 0xBF;
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sfr IRCON = 0xC0;
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sfr CCEN = 0xC1;
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sfr CCL1 = 0xC2;
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sfr CCH1 = 0xC3;
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sfr CCL2 = 0xC4;
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sfr CCH2 = 0xC5;
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sfr CCL3 = 0xC6;
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sfr CCH3 = 0xC7;
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sfr T2CON = 0xC8;
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sfr CRCL = 0xCA;
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sfr CRCH = 0xCB;
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sfr TL2 = 0xCC;
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sfr TH2 = 0xCD;
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sfr CLKPRE = 0xD2;
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sfr RSTCON = 0xD3;
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sfr KEY_CTL = 0xD7;
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sfr ADCON = 0xD8;
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sfr RST_FLAG = 0xE1;
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sfr CHIP_STA0 = 0xE2;
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sfr CHIP_STA1 = 0xE3;
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sfr CHIP_STA2 = 0xE4;
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sfr CHIP_STA3 = 0xE5;
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sfr CHIP_STA4 = 0xE6;
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sfr IRQ_FLAG0 = 0xE8;
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sfr IRQ_FLAG1 = 0xE9;
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sfr IRQ_FLAG2 = 0xEA;
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sfr IRQ_FLAG3 = 0xEB;
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sfr IRQ_FLAG4 = 0xEC;
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sfr IRQ_FLAG7 = 0xEF;
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sfr IRQ_FLAG9 = 0xF2;
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sfr IRQ_FLAG10 = 0xF3;
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sfr SRST = 0xF7;
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sfr WKUP_FLAG0 = 0xF6;
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sfr WKUP_FLAG1 = 0xF8;
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sfr WKUP_FLAG3 = 0xFA;
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sfr SFRADDR = 0xFE;
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sfr SFRDATA = 0xFF;
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/*--- BIT Register ---*/
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/* PSW */
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sbit CY = 0xD7;
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sbit AC = 0xD6;
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sbit F0 = 0xD5;
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sbit RS1 = 0xD4;
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sbit RS0 = 0xD3;
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sbit OV = 0xD2;
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sbit P = 0xD0;
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/* TCON */
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sbit TF1 = 0x8F;
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sbit TR1 = 0x8E;
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sbit TF0 = 0x8D;
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sbit TR0 = 0x8C;
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sbit IE1 = 0x8B;
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sbit IT1 = 0x8A;
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sbit IE0 = 0x89;
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sbit IT0 = 0x88;
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/* T2CON */
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sbit T2PS = 0xCF;
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sbit I3FR = 0xCE;
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sbit I2FR = 0xCD;
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sbit T2R1 = 0xCC;
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sbit T2R0 = 0xCB;
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sbit T2CM = 0xCA;
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sbit T2I1 = 0xC9;
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sbit T2I0 = 0xC8;
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/* S0CON */
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sbit SM0 = 0x9F;
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sbit SM1 = 0x9E;
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sbit SM20 = 0x9D;
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sbit REN0 = 0x9C;
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sbit TB80 = 0x9B;
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sbit RB80 = 0x9A;
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sbit TI0 = 0x99;
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sbit RI0 = 0x98;
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/* IEN0 */
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sbit EAL = 0xAF;
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sbit WDT = 0xAE;
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sbit ET2 = 0xAD;
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sbit ES0 = 0xAC;
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sbit ET1 = 0xAB;
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sbit EX1 = 0xAA;
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sbit ET0 = 0xA9;
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sbit EX0 = 0xA8;
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/* IEN1 */
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sbit EXEN2 = 0xBF;
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sbit SWDT = 0xBE;
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sbit EX6 = 0xBD;
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sbit EX5 = 0xBC;
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sbit EX4 = 0xBB;
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sbit EX3 = 0xBA;
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sbit EX2 = 0xB9;
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sbit EX7 = 0xB8;
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/* IRCON */
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sbit EXF2 = 0xC7;
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sbit TF2 = 0xC6;
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sbit IEX6 = 0xC5;
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sbit IEX5 = 0xC4;
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sbit IEX4 = 0xC3;
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sbit IEX3 = 0xC2;
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sbit IEX2 = 0xC1;
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sbit IADC = 0xC0;
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/* ADCON */
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sbit BD = 0xDF;
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/* P0 */
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sbit P00 = P0^0;
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sbit P01 = P0^1;
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sbit P02 = P0^2;
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sbit P03 = P0^3;
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sbit P04 = P0^4;
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sbit P05 = P0^5;
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sbit P06 = P0^6;
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sbit P07 = P0^7;
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/* P1 */
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sbit P10 = P1^0;
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#endif
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